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EC3561 - VLSI Laboratory Syllabus Regulation 2021 Anna University

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Code EC3561 deals with the subject from the Anna University Regulation 2021, related to affiliated institutions, syllabus of B.E Electronics and Telecommunication Engineering. In this article, we discuss the VLSI Laboratory Syllabus.

We intend to provide the syllabus of EC3561 – VLSI Laboratory, we include the textbooks and references from the faculty of experts. You can get the required information unit-wise. The following links will help you to get proper information. I hope you can find the details in the article given below.

If you want to know more about the syllabus of B.E Computer Science and Engineering (Cyber security) Syllabus connected to an affiliated institution’s four-year undergraduate degree program. We provide you with a detailed Year-wise, semester-wise, and Subject-wise syllabus in the following link B.E Electronics and Telecommunication Engineering Syllabus Anna University, Regulation 2021.

Aim of Objectives:

  • To learn Hardware Descriptive Language (Verilog/VHDL).
  • To learn the fundamental principles of Digital System design using HDL and FPGA.
  • To learn the fundamental principles of VLSI circuit design in digital domain.
  • To learn the fundamental principles of VLSI circuit design in analog domain.
  • To provide hands-on design experience with EDA platforms.

List Of Experiments:

  1. Design of basic combinational and sequential (Flip-flops) circuits using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA.
  2. Design an Adder; Multiplier (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA.
  3. Design and implement a Universal Shift Register using HDL. Simulate it using Xilinx/Altera Software.
  4. Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA.
  5. Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA.
  6. Design a 3-bit synchronous up/down counter using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA.
  7. Design a 4-bit Asynchronous up/down counter using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA.
  8. Design and simulate a CMOS Basic Gates & Flip-Flops. Generate Manual/Automatic Layout.
  9. Design and simulate a 4-bit synchronous counter using a Flip-Flops. Generate Manual/Automatic Layout.
  10. Design and Simulate a CMOS Inverting Amplifier.
  11. Design and Simulate basic Common Source, Common Gate and Common Drain Amplifiers.
  12. Design and simulate a simple 5-transistor differential amplifier.

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