Code EC3352 deals with the subject from the Anna University Regulation 2021, related to affiliated institutions, syllabus of B.E Electronics and Telecommunication Engineering. In this article, we discuss the Digital Systems Design Syllabus.
We intend to provide the syllabus of EC3352 – Digital Systems Design, we include the textbooks and references from the faculty of experts. You can get the required information unit-wise. The following links will help you to get proper information. I hope you can find the details in the article given below.
If you want to know more about the syllabus of B.E Computer Science and Engineering (Cyber security) Syllabus connected to an affiliated institution’s four-year undergraduate degree program. We provide you with a detailed Year-wise, semester-wise, and Subject-wise syllabus in the following link B.E Electronics and Telecommunication Engineering Syllabus Anna University, Regulation 2021.
Aim of Objectives:
- To present the fundamentals of digital circuits and simplification methods.
- To practice the design of various combinational digital circuits using logic gates.
- To bring out the analysis and design procedures for synchronous and asynchronous Sequential circuits.
- To learn integrated circuit families.
- To introduce semiconductor memories and related technology.
EC3352 – Digital Systems Design Syllabus
Unit – I: Basic Concepts
Review of number systems – representation – conversions, Review of Boolean algebra – theorems, sum of product and product of sum simplification, canonical forms min term and max term, Simplification of Boolean expressions – Karnaugh map, completely and incompletely specified functions, Implementation of Boolean expressions using universal gates, Tabulation methods.
Unit – II: Combinational Logic Circuits
Problem formulation and design of combinational circuits – Code-Converters, Half and Full Adders, Binary Parallel Adder – Carry look ahead Adder, BCD Adder, Magnitude Comparator, Decoder, Encoder, Priority Encoder, Mux/Demux, Case study: Digital trans-receiver / 8-bit Arithmetic and logic unit, Parity Generator/Checker, Seven Segment display decoder.
Unit – III: Synchronous Sequential Circuits
Latches, Flip flops – SR, JK, T, D, Master/Slave FF, Triggering of FF, Analysis and design of clocked sequential circuits – Design – Moore/Mealy models, state minimization, state assignment, lock-out condition circuit implementation – Counters, Ripple Counters, Ring Counters, Shift registers, Universal Shift Register. Model Development: Designing of rolling display/real-time clock.
Unit – IV: Asynchronous Sequential Circuits
Stable and Unstable states, output specifications, cycles and races, state reduction, race-free assignments, Hazards, Essential Hazards, Fundamental and Pulse mode sequential circuits, Design of Hazard free circuits.
Unit – V: Logic Families And Programmable Logic Devices
Logic families- Propagation Delay, Fan-In and Fan-Out – Noise Margin – RTL, TTL, ECL CMOS – Comparison of Logic families – Implementation of combinational logic/sequential logic design using standard ICs, PROM, PLA and PAL, basic memory, static ROM, PROM, EPROM, EEPROM EAPROM.
Text Books:
- M. Morris Mano and Michael D. Ciletti, ‘Digital Design’, Pearson, 5th Edition, 2013. (Unit – IV)
References:
- Charles H. Roth, Jr, ‘Fundamentals of Logic Design’, Jaico Books, 4th Edition, 2002.
- William I. Fletcher, “An Engineering Approach to Digital Design”, Prentice-Hall of India, 1980.
- Floyd T.L., “Digital Fundamentals”, Charles E. Merril publishing company, 1982.
- John. F. Wakerly, “Digital Design Principles and Practices”, Pearson Education, 4th Edition,2007.
Related posts on Semester – III:
- MA3355 Random Processes and Linear Algebra
- CS3353 C Programming and Data Structures
- EC3354 Signals and Systems
- EC3353 Electronic Devices and Circuits
- EC3351 Control Systems
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